OpenBlockS の MPC860 内部設定

$Id: mpc860.html,v 1.2 2003/07/11 16:30:16 murase Exp $

CPU である MPC860 の内部設定を調べた結果です。放置プレイ中。

System Interface Unit
Memory Controller
System integration timers
Clocks and reset
CPM: SI and TSA

クロック

外部設定
pin	input
MODCK[1-2]	"11"	x5 clock mode(default)
EXTCLK	4.096[MHz]

内部クロック
Clk Freq. Description
OSCCLK 4.096 [MHz]
VCOOUT 49.152 [MHz] OSCCLK x (11 + 1)
GCLK1/2/C 49.152 [MHz]
GCLK1/2_50 49.152 [MHz]
CLKOUT 49.152 [MHz]
BRGCLK 49.152 [MHz]
SYNCCLK 49.152 [MHz]
TMBCLK 3.072 [MHz] GCLK2 / 16
PITRTCLK 8.000 [kHz] EXTCLK / 512

内部クロック
Clk	Freq.	Description
OSCCLK	4.096 [MHz]
VCOOUT	49.152 [MHz]	OSCCLK x (11 + 1)
GCLK1/2/C	49.152 [MHz]
GCLK1/2_50	49.152 [MHz]
CLKOUT	49.152 [MHz]
BRGCLK	49.152 [MHz]
SYNCCLK	49.152 [MHz]
TMBCLK	3.072 [MHz]	GCLK2 / 16
PITRTCLK	8.000 [kHz]	EXTCLK / 512

割り込み

see /proc/interrupt.

No.	Source	Assign	Description
0	IRQ0
1	LEVEL0
2	IRQ1
3	LEVEL1	fec	100Base-TX MAC
4	IRQ2	pushswitch	INITスイッチ (未確認)
5	LEVEL2	cpm	Serial, etc.
6	IRQ3
7	LEVEL3
8	IRQ4	ide0	hda ???
9	LEVEL4
10	IRQ5	mii	100Base-TX PHY
11	LEVEL5
12	IRQ6
13	LEVEL6
14	IRQ7		MPC860Tでは使用不可
15	LEVEL7	tbint	Timebase

I/O ポート

PortA	PAR=0 DIR=0:IN 1:OUT	PAR=1 DIR=0	PAR=1 DIR=1	説明
PA15		RXD1		ttyS1
PA14		TXD1		ttyS1
PA13		RXD2		eth1
PA12		TXD2		eth1
PA11	OUTPUT			ttyS1 DTR 0:ON 1:OFF
PA10	INPUT			INITスイッチ 0:ON 1:OFF
PA9	INPUT			eth1 LEDL
PA8	INPUT			eth1 LEDC
PA7		CLK1		eth1 TCLK
PA6		CLK2		eth1 RCLK
PA5
PA4	OUTPUT			eth1 loopback control 0:Normal 1:Loopback
PA3
PA2		CLK6		7.3728[MHz] for ttyS1 ???
PA1	INPUT			SW1-1 0:ON 1:OFF
PA0	INPUT			SW1-2 0:ON 1:OFF

7セグLED ---- データ値 0:ON 1:OFF

b14

---

b16 | | b15

| b3 |

---

b1 | | b17

| b0 |

--- o b2
適当に作った定義ファイル。

PortB	PAR=0 DIR=0:IN 1:OUT	PAR=1 DIR=0	PAR=1 DIR=1	説明
PB31	OUTPUT			7SEG-b0
PB30	OUTPUT			7SEG-b1
PB29	OUTPUT			7SEG-b2
PB28	OUTPUT			7SEG-b3
PB27			I2CSDA	ODR=1
PB26			I2CSCL	ODR=1
PB25		SMTXD1
PB24		SMRXD1
PB23
PB22
PB21
PB20
PB19	OUTPUT(RTS1)			ttyS1 RTS 0:ON 1:OFF
PB18			RTS2	TENA
PB17	OUTPUT			7SEG-b14
PB16	OUTPUT			7SEG-b15
PB15	OUTPUT			7SEG-b16
PB14	OUTPUT			7SEG-b17

PortC	PAR=0 DIR=0:IN 1:OUT or SO=0	PAR=0 DIR=0 and SO=1	PAR=1 DIR=0	PAR=1 DIR=1	説明
PC15
PC14
PC13	INPUT(DSR1)				ttyS1 DSR
PC12	OUTPUT				IDE RESET 0:ON 1:OFF
PC11	INPUT(CTS1)				ttyS1 CTS
PC10	INPUT(CD1)				ttyS1 CD
PC9		CTS2			CLSN
PC8		CD2			RENA
PC7
PC6
PC5
PC4

SIUMCR
Address 0xff000000
Value 0x00010640
Bits Name Value Description
MSB(0) EARB 0 Internal arbitration is permitted.
1:3 EARP 0b000 External arbitration request priority.
4:7 ---- 0b0000 Reserved.
8 DSHW 0 Data show cycles. Disabled.
9:10 DBGC 0b00 Debug pins config.
IP_B[0-1], OP2, ALE_B, IP_B2, IP_B6, IP_B7, OP3
11:12 DBPC 0b00 Debug port pins config.
DSCK, DSDI, DSDO
13 - 0 Reserved.
14 FRC 0 FRZ pin config. FRZ/-IRQ6 is FRZ.
15 DLK 1 Debug register lock.
16 OPAR 0 0:Even parity. 1:Odd parity.
17 PNCS 0 Parity enable for nonmemory controller regions. Off.
18 DPC 0 Data parity pins config. DP[0-3] as -IRQ[3-6]
19 MPRE 0 Multiprocessors reservation. RSV/IRQ2 as -IRQ2.
20:21 MLRC 0 Multi-level reservation control. KR as -IRQ4.
22 AEME 1 Asynchronous external master enable.
23 SEME 1 Synchronous external master enable.
24 BSC 0 Byte selects ans strobes.
BS_A[0-3],
WE0/BS_B0/IORD
WE1/BS_B1/IOWR
WE2/BS_B2/PCOE
WE3/BS_B3/PCWE
25 GB5E 1 -GPL_B5 enable.
26 B2DD 0 Bank 2 double drive. Off.
27 B3DD 0 Bank 3 double drive. Off.
28:LSB(31) ---- 0b0000 Reserved.

SIUMCR
Address	0xff000000
Value	0x00010640
Bits	Name	Value	Description
MSB(0)	EARB	0	Internal arbitration is permitted.
1:3	EARP	0b000	External arbitration request priority.
4:7	----	0b0000	Reserved.
8	DSHW	0	Data show cycles. Disabled.
9:10	DBGC	0b00	Debug pins config. IP_B[0-1], OP2, ALE_B, IP_B2, IP_B6, IP_B7, OP3
11:12	DBPC	0b00	Debug port pins config. DSCK, DSDI, DSDO
13	-	0	Reserved.
14	FRC	0	FRZ pin config. FRZ/-IRQ6 is FRZ.
15	DLK	1	Debug register lock.
16	OPAR	0	0:Even parity. 1:Odd parity.
17	PNCS	0	Parity enable for nonmemory controller regions. Off.
18	DPC	0	Data parity pins config. DP[0-3] as -IRQ[3-6]
19	MPRE	0	Multiprocessors reservation. RSV/IRQ2 as -IRQ2.
20:21	MLRC	0	Multi-level reservation control. KR as -IRQ4.
22	AEME	1	Asynchronous external master enable.
23	SEME	1	Synchronous external master enable.
24	BSC	0	Byte selects ans strobes. BS_A[0-3], WE0/BS_B0/IORD WE1/BS_B1/IOWR WE2/BS_B2/PCOE WE3/BS_B3/PCWE
25	GB5E	1	-GPL_B5 enable.
26	B2DD	0	Bank 2 double drive. Off.
27	B3DD	0	Bank 3 double drive. Off.
28:LSB(31)	----	0b0000	Reserved.

SYPCR
Address 0xff000004
Value 0xffffff07
Bits Name Value Description
MSB(0):15 SWTC 0xffff Software watchdog timer count.
16:23 BMT 0xff Bus monitor timing.
24 BME 0 Bus monitor disable(0).
25:27 --- 0b000 Reserved.
28 SWF 0 Software watchdog timer continues counting even if FRZ(0).
29 SWE 1 Software watchdog timer enable(1).
30 SWRI 1 Software watchdog timer causes an HRESET(1).
LSB(31) SWP 1 Software watchdog timer is prescaled by a factor of 2048.

SYPCR
Address	0xff000004
Value	0xffffff07
Bits	Name	Value	Description
MSB(0):15	SWTC	0xffff	Software watchdog timer count.
16:23	BMT	0xff	Bus monitor timing.
24	BME	0	Bus monitor disable(0).
25:27	---	0b000	Reserved.
28	SWF	0	Software watchdog timer continues counting even if FRZ(0).
29	SWE	1	Software watchdog timer enable(1).
30	SWRI	1	Software watchdog timer causes an HRESET(1).
LSB(31)	SWP	1	Software watchdog timer is prescaled by a factor of 2048.

SIPEND
Address 0xff000010
Value 0x00000000
Bits Name Value Description
MSB(0) IRQ0 0 IRQ pending.
1 LVL0 0 Level interrupt pending.
2 IRQ1 0 IRQ pending.
3 LVL1 0 Level interrupt pending.
4 IRQ2 0 IRQ pending.
5 LVL2 0 Level interrupt pending.
6 IRQ3 0 IRQ pending.
7 LVL3 0 Level interrupt pending.
8 IRQ4 0 IRQ pending.
9 LVL4 0 Level interrupt pending.
10 IRQ5 0 IRQ pending.
11 LVL5 0 Level interrupt pending.
12 IRQ6 0 IRQ pending.
13 LVL6 0 Level interrupt pending.
14 IRQ7 0 IRQ pending.
15 LVL7 0 Level interrupt pending.
16:LSB(31) ---- 0x0000 Reserved.

SIPEND
Address	0xff000010
Value	0x00000000
Bits	Name	Value	Description
MSB(0)	IRQ0	0	IRQ pending.
1	LVL0	0	Level interrupt pending.
2	IRQ1	0	IRQ pending.
3	LVL1	0	Level interrupt pending.
4	IRQ2	0	IRQ pending.
5	LVL2	0	Level interrupt pending.
6	IRQ3	0	IRQ pending.
7	LVL3	0	Level interrupt pending.
8	IRQ4	0	IRQ pending.
9	LVL4	0	Level interrupt pending.
10	IRQ5	0	IRQ pending.
11	LVL5	0	Level interrupt pending.
12	IRQ6	0	IRQ pending.
13	LVL6	0	Level interrupt pending.
14	IRQ7	0	IRQ pending.
15	LVL7	0	Level interrupt pending.
16:LSB(31)	----	0x0000	Reserved.

SIMASK
Address 0xff000014
Value 0x1ca10000
Bits Name Value Description
MSB(0) IRQ0 0 Enable updating SIVEC..
1 LVL0 0 Level interrupt mask(0).
2 IRQ1 0 IRQ mask(0).
3 LVL1 1 Level interrupt mask(0).
4 IRQ2 1 IRQ mask(0).
5 LVL2 1 Level interrupt mask(0).
6 IRQ3 0 IRQ mask(0).
7 LVL3 0 Level interrupt mask(0).
8 IRQ4 1 IRQ mask(0).
9 LVL4 0 Level interrupt mask(0).
10 IRQ5 1 IRQ mask(0).
11 LVL5 0 Level interrupt mask(0).
12 IRQ6 0 IRQ mask(0).
13 LVL6 0 Level interrupt mask(0).
14 IRQ7 0 IRQ mask(0).
15 LVL7 1 Level interrupt mask(0).
16:LSB(31) ---- 0x0000 Reserved.
note. Interrupt 1:enable. 0:disable(mask)

SIMASK
Address	0xff000014
Value	0x1ca10000
Bits	Name	Value	Description
MSB(0)	IRQ0	0	Enable updating SIVEC..
1	LVL0	0	Level interrupt mask(0).
2	IRQ1	0	IRQ mask(0).
3	LVL1	1	Level interrupt mask(0).
4	IRQ2	1	IRQ mask(0).
5	LVL2	1	Level interrupt mask(0).
6	IRQ3	0	IRQ mask(0).
7	LVL3	0	Level interrupt mask(0).
8	IRQ4	1	IRQ mask(0).
9	LVL4	0	Level interrupt mask(0).
10	IRQ5	1	IRQ mask(0).
11	LVL5	0	Level interrupt mask(0).
12	IRQ6	0	IRQ mask(0).
13	LVL6	0	Level interrupt mask(0).
14	IRQ7	0	IRQ mask(0).
15	LVL7	1	Level interrupt mask(0).
16:LSB(31)	----	0x0000	Reserved.

SIEL
Address 0xff000018
Value 0x8c200000
Bits Name Value Description
MSB(0) ED0 1 IRQ0 Edge detect..
1 WM0 0 IRQ0 Wake up from low-power mode.
2 ED1 0 IRQ1 Edge ...
3 WM1 0 IRQ1 Wake up ...
4 ED2 1 :
5 WM2 1 :
6 ED3 0 :
7 WM3 0 :
8 ED4 0 :
9 WM4 0 :
10 ED5 1 :
11 WM5 0 :
12 ED6 0 :
13 WM6 0 :
14 ED7 0 IRQ0 Edge ...
15 WM7 0 IRQ0 Wake up ...
16:LSB(31) ---- 0x0000 Reserved.

SIEL
Address	0xff000018
Value	0x8c200000
Bits	Name	Value	Description
MSB(0)	ED0	1	IRQ0 Edge detect..
1	WM0	0	IRQ0 Wake up from low-power mode.
2	ED1	0	IRQ1 Edge ...
3	WM1	0	IRQ1 Wake up ...
4	ED2	1	:
5	WM2	1	:
6	ED3	0	:
7	WM3	0	:
8	ED4	0	:
9	WM4	0	:
10	ED5	1	:
11	WM5	0	:
12	ED6	0	:
13	WM6	0	:
14	ED7	0	IRQ0 Edge ...
15	WM7	0	IRQ0 Wake up ...
16:LSB(31)	----	0x0000	Reserved.

SIVEC
Address 0xff00001c
Value 0x--000000
Bits Name Value Description
MSB(0):7 INTC 0x-- Interrupt code.
8:LSB(31) ---- 0x000000 Reserved.

SIVEC
Address	0xff00001c
Value	0x--000000
Bits	Name	Value	Description
MSB(0):7	INTC	0x--	Interrupt code.
8:LSB(31)	----	0x000000	Reserved.

SDCR
Address 0xff000030
Value 0x00000001
Bits Name Value Description
MSB(0):15 ---- 0x0000 Reserved.
17 FRZ 0 Freeze.
18:29 --- 0 Reserved.
30:LSB(31) RAID 0b01 Priority level 5 (BR5).

SDCR
Address	0xff000030
Value	0x00000001
Bits	Name	Value	Description
MSB(0):15	----	0x0000	Reserved.
17	FRZ	0	Freeze.
18:29	---	0	Reserved.
30:LSB(31)	RAID	0b01	Priority level 5 (BR5).

Memory Controller

memc_br0	ff000100 ffc00801
memc_or0	ff000104 ffe00952
memc_br1	ff000108 ffe00801
memc_or1	ff00010c ffe00952
memc_br2	ff000110 00000081
memc_or2	ff000114 ff000c00
memc_br3	ff000118 01000801
memc_or3	ff00011c ff000952
memc_br4	ff000120 80000801
memc_or4	ff000124 ffc00d28
memc_br5	ff000128 54932980
memc_or5	ff00012c 140112fa
memc_br6	ff000130 40fd1780
memc_or6	ff000134 20428180
memc_br7	ff000138 0e98b7c0
memc_or7	ff00013c 11842d36
memc_mar	ff000164 00000088
memc_mcr	ff000168 80004106
memc_mamr	ff000170 18802111
memc_mbmr	ff000174 81001000
memc_mstat	ff000178 0000
memc_mptpr	ff00017a 0200
memc_mdr	ff00017c fffffc04

System integration timers

TBSCR
PISCR

tbscr	ff000200 01c3
tbreff0	ff000204 ffffffff
tbreff1	ff000208 ffffffff
rtcsc	ff000220 0091
rtc	ff000224 3b10fa66
rtsec	ff000228 0fac0000
rtcal	ff00022c ffffffff
piscr	ff000240 0000
pitc	ff000244 ffff0000
pitr	ff000248 ffff0000

TBSCR
Address 0xff000200
Value 0x01c3
Bits Name Value Description
MSB(0):7 TBIRQ 0x01 Timebase interrupt request level.
8 REFA 1 Reference interrupt status.
9 REFB 1 Reference interrupt status.
10:11 -- 0b00 Reserved.
12 REFAE 0 Reference interrupt enable A.
13 REFBE 0 Reference interrupt enable B.
14 TBF 1 Timebase freeze enable.
LSB(15) TBE 1 Timebase enable.

TBSCR
Address	0xff000200
Value	0x01c3
Bits	Name	Value	Description
MSB(0):7	TBIRQ	0x01	Timebase interrupt request level.
8	REFA	1	Reference interrupt status.
9	REFB	1	Reference interrupt status.
10:11	--	0b00	Reserved.
12	REFAE	0	Reference interrupt enable A.
13	REFBE	0	Reference interrupt enable B.
14	TBF	1	Timebase freeze enable.
LSB(15)	TBE	1	Timebase enable.

PISCR
Address 0xff000240
Value 0x0000
Bits Name Value Description
MSB(0):7 PIIRQ 0x01 Periodic interrupt request level.
8 PS 0x00 Periodic interrupt status.
9:12 ---- 0b0000 Reserved.
13 PIE 0 Periodic interrupt enable.
14 PITF 0 PIT freeze enable.
LSB(15) PTE 0 Periodic timer enable.

PISCR
Address	0xff000240
Value	0x0000
Bits	Name	Value	Description
MSB(0):7	PIIRQ	0x01	Periodic interrupt request level.
8	PS	0x00	Periodic interrupt status.
9:12	----	0b0000	Reserved.
13	PIE	0	Periodic interrupt enable.
14	PITF	0	PIT freeze enable.
LSB(15)	PTE	0	Periodic timer enable.

Clocks and reset

SCCR
PLPRCR
RSR

car_sccr	ff000280 03800000
car_plprcr	ff000284 00b05000
car_rsr	ff000288 c0000000

SCCR
Address 0xff000280
Value 0x03800000
Bits Name Value Description
MSB(0) - 0 Reserved.
1:2 COM 0b00 Clock Output Module.
3:5 --- 0b000 Reserved.
6 TBS 1 Timebase Source. GCLK2 / 16.
7 RTDIV 1 Real-Time Clock Divide. / 512.
8 RTSEL 1 Real-Time Clock Select. EXTCLK.
9 CRQEN 0 CPM Request Enable.
10 PRQEN 0 Power Management Request Enable.
11:12 -- 0b00 Reserved.
13:14 EBDF 0b00 External Bus Division Factor.
15 - 0 Reserved.
16 - 0 Reserves.
17:18 DFSYNC 0b00 Division Factor of the SYNCCLK. /1.
19:20 DFBRG 0b00 Division Factor of the BRGCLK. /1.
21:23 DFNL 0b000 Division Factor low frequency. /2.
24:26 DFNH 0b000 Division Factor high frequency. /1.
27:LSB(31) ----- 0b00000 Reserved.

SCCR
Address	0xff000280
Value	0x03800000
Bits	Name	Value	Description
MSB(0)	-	0	Reserved.
1:2	COM	0b00	Clock Output Module.
3:5	---	0b000	Reserved.
6	TBS	1	Timebase Source. GCLK2 / 16.
7	RTDIV	1	Real-Time Clock Divide. / 512.
8	RTSEL	1	Real-Time Clock Select. EXTCLK.
9	CRQEN	0	CPM Request Enable.
10	PRQEN	0	Power Management Request Enable.
11:12	--	0b00	Reserved.
13:14	EBDF	0b00	External Bus Division Factor.
15	-	0	Reserved.
16	-	0	Reserves.
17:18	DFSYNC	0b00	Division Factor of the SYNCCLK. /1.
19:20	DFBRG	0b00	Division Factor of the BRGCLK. /1.
21:23	DFNL	0b000	Division Factor low frequency. /2.
24:26	DFNH	0b000	Division Factor high frequency. /1.
27:LSB(31)	-----	0b00000	Reserved.

PLPRCR
Address 0xff000284
Value 0x00b05000
Bits Name Value Description
MSB(0):11 MF 0x00b Multiplication factor.
12:15 ---- 0x0 Reserved.
16 SPLSS 0 System PLL Lock Status Sticky.
17 TEXPS 1 Timer Expired Status.
18 - 0 Reserved.
19 TMIST 1 Timers Interrupt status.
20 - 0 Reserved.
21 CSRC 0 Clock source.
22:23 LPM 0 Low-power modes.
24 CSR 0 Checkstop reset enable.
25 LOLRE 0 Loss-of-lock reset enable.
26 FIOPD 0 Force I/O pull down.
27:LSB(31) ----- 0b00000 Reserved.

PLPRCR
Address	0xff000284
Value	0x00b05000
Bits	Name	Value	Description
MSB(0):11	MF	0x00b	Multiplication factor.
12:15	----	0x0	Reserved.
16	SPLSS	0	System PLL Lock Status Sticky.
17	TEXPS	1	Timer Expired Status.
18	-	0	Reserved.
19	TMIST	1	Timers Interrupt status.
20	-	0	Reserved.
21	CSRC	0	Clock source.
22:23	LPM	0	Low-power modes.
24	CSR	0	Checkstop reset enable.
25	LOLRE	0	Loss-of-lock reset enable.
26	FIOPD	0	Force I/O pull down.
27:LSB(31)	-----	0b00000	Reserved.

CPM: Serial Interface and Time Slot Assignment

SICR

SICR
Address 0xff000aec
Value 0x001b2c09
Bits Name Value Description
MSB(0) GR4 0 Gtant support of SCC.
1 SC4 0 SCC connection.
2:4 R4CS 0b000 Receive clock source for SCC.(BRG1)
5:7 T4CS 0b000 Transmit clock source for SCC.(BRG1)
8 GR3 0 Gtant support of SCC.
9 SC3 0 SCC connection.
10:12 R3CS 0b011 Receive clock source for SCC.(BRG4)
13:15 T3CS 0b011 Transmit clock source for SCC.(BRG4)
16 GR2 0 Gtant support of SCC.
17 SC2 0 SCC connection.
18:20 R2CS 0b101 Receive clock source for SCC.(CLK2)
21:23 T2CS 0b100 Transmit clock source for SCC.(CLK1)
24 GR1 0 Gtant support of SCC.
25 SC1 0 SCC connection.
26:28 R1CS 0b001 Receive clock source for SCC.(BRG2)
29:LSB(31) T1CS 0b001 Transmit clock source for SCC.(BRG2)

SICR
Address	0xff000aec
Value	0x001b2c09
Bits	Name	Value	Description
MSB(0)	GR4	0	Gtant support of SCC.
1	SC4	0	SCC connection.
2:4	R4CS	0b000	Receive clock source for SCC.(BRG1)
5:7	T4CS	0b000	Transmit clock source for SCC.(BRG1)
8	GR3	0	Gtant support of SCC.
9	SC3	0	SCC connection.
10:12	R3CS	0b011	Receive clock source for SCC.(BRG4)
13:15	T3CS	0b011	Transmit clock source for SCC.(BRG4)
16	GR2	0	Gtant support of SCC.
17	SC2	0	SCC connection.
18:20	R2CS	0b101	Receive clock source for SCC.(CLK2)
21:23	T2CS	0b100	Transmit clock source for SCC.(CLK1)
24	GR1	0	Gtant support of SCC.
25	SC1	0	SCC connection.
26:28	R1CS	0b001	Receive clock source for SCC.(BRG2)
29:LSB(31)	T1CS	0b001	Transmit clock source for SCC.(BRG2)

katsunori.murase@nifty.ne.jp

		b14
		---
b16	\|		\|	b15
	\|	b3	\|
		---
b1	\|		\|	b17
	\|	b0	\|
		---	o	b2