diff -Nru gdb-5.0/gdb/config/h8300/tm-h8300.h gdb-5.0-patch/gdb/config/h8300/tm-h8300.h --- gdb-5.0/gdb/config/h8300/tm-h8300.h Tue Dec 14 10:05:40 1999 +++ gdb-5.0-patch/gdb/config/h8300/tm-h8300.h Tue Sep 25 10:27:05 2001 @@ -84,7 +84,7 @@ #define INNER_THAN(lhs,rhs) ((lhs) < (rhs)) /*#define BREAKPOINT {0x7A, 0xFF} */ -#define BREAKPOINT {0x01, 0x80} /* Sleep */ +#define BREAKPOINT {0x01, 0x81} /* bkpt(?) */ #define REMOTE_BREAKPOINT { 0x57, 0x30} /* trapa #3 */ /* If your kernel resets the pc after the trap happens you may need to define this before including this file. */ diff -Nru gdb-5.0/include/opcode/h8300.h gdb-5.0-patch/include/opcode/h8300.h --- gdb-5.0/include/opcode/h8300.h Mon May 3 16:29:05 1999 +++ gdb-5.0-patch/include/opcode/h8300.h Tue Sep 25 10:27:23 2001 @@ -303,7 +303,8 @@ #define O_LDM 85 #define O_STM 86 #define O_STMAC 87 -#define O_LAST 88 +#define O_BKPT 88 +#define O_LAST 89 #define SB 0 #define SW 1 #define SL 2 @@ -321,6 +322,10 @@ NEW_SOP(O(O_ADD,SW),0,4,"add.w"),{{IMM16,RD16,E}},{{0x7,0x9,0x1,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP, NEW_SOP(O(O_ADD,SL),0,2,"add.l"),{{RS32,RD32,E }}, {{0x0,0xA,B31|RS32,B30|RD32,E}} EOP, NEW_SOP(O(O_ADD,SL),0,6,"add.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x1,B30|RD32,IMM32LIST,E}} EOP, + + NEW_SOP(O(O_INC,SL),0,2,"inc.l") ,{{DBIT,RD32,E }},{{0x0,0xB,0x7|DBIT,RD32|B30,E}} EOP, + NEW_SOP(O(O_INC,SW),0,2,"inc.w") ,{{DBIT,RD16,E }},{{0x0,0xB,0x5|DBIT,RD16,E}} EOP, + NEW_SOP(O(O_ADDS,SL),1,2,"adds"), {{KBIT,RDP,E}}, {{0x0,0xB,KBIT,RDP,E,0,0,0,0}} EOP, TWOOP(O(O_ADDX,SB),"addx",0x9,0x0,0xE), @@ -374,6 +379,8 @@ EBITOP(O(O_BTST,SB), IMM3|B30,"btst",0x6,0x3,0x7,0xC,0x7,0xE,0x0), BITOP(O(O_BXOR,SB), IMM3|B30,"bxor",0x7,0x5,0x7,0xC,0x7,0xE,0x0), + SOP(O(O_BKPT,SN),2,"bkpt"),{{E,0,0}},{{ 0x0,0x1,0x8,0x1,E,0,0,0,0}} EOP, + TWOOP(O(O_CMP,SB), "cmp.b",0xA,0x1,0xC), WTWOP(O(O_CMP,SW), "cmp.w",0x1,0xD), @@ -387,8 +394,8 @@ UNOP(O(O_DAS,SB), "das",0x1,0xF), UNOP(O(O_DEC,SB), "dec.b",0x1,0xA), - NEW_SOP(O(O_DEC, SW),0,2,"dec.w") ,{{DBIT,RD16,E }},{{0x1,0xB,0x5|DBIT,RD16,E}} EOP, NEW_SOP(O(O_DEC, SL),0,2,"dec.l") ,{{DBIT,RD32,E }},{{0x1,0xB,0x7|DBIT,RD32|B30,E}} EOP, + NEW_SOP(O(O_DEC, SW),0,2,"dec.w") ,{{DBIT,RD16,E }},{{0x1,0xB,0x5|DBIT,RD16,E}} EOP, NEW_SOP(O(O_DIVU,SB),1,6,"divxu.b"), {{RS8,RD16,E}}, {{0x5,0x1,RS8,RD16,E,0,0,0,0}}EOP, NEW_SOP(O(O_DIVU,SW),0,20,"divxu.w"),{{RS16,RD32,E}},{{0x5,0x3,RS16,B30|RD32,E}}EOP, @@ -407,9 +414,6 @@ UNOP(O(O_INC,SB), "inc",0x0,0xA), - NEW_SOP(O(O_INC,SW),0,2,"inc.w") ,{{DBIT,RD16,E }},{{0x0,0xB,0x5|DBIT,RD16,E}} EOP, - NEW_SOP(O(O_INC,SL),0,2,"inc.l") ,{{DBIT,RD32,E }},{{0x0,0xB,0x7|DBIT,RD32|B30,E}} EOP, - SOP(O(O_JMP,SB),4,"jmp"),{{RSIND,E,0}},{{0x5,0x9,B30|RSIND,0x0,E,0,0,0,0}}EOP, SOP(O(O_JMP,SB),6,"jmp"),{{SRC|ABSJMP,E,0}},{{0x5,0xA,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}}EOP, SOP(O(O_JMP,SB),8,"jmp"),{{SRC|MEMIND,E,0}},{{0x5,0xB,SRC|MEMIND,IGNORE,E,0,0,0,0}}EOP, diff -Nru gdb-5.0/sim/h8300/compile.c gdb-5.0-patch/sim/h8300/compile.c --- gdb-5.0/sim/h8300/compile.c Tue Apr 27 03:32:21 1999 +++ gdb-5.0-patch/sim/h8300/compile.c Tue Sep 25 10:27:15 2001 @@ -82,7 +82,7 @@ #define HIGH_BYTE(x) (((x)>>8) & 0xff) #define P(X,Y) ((X<<8) | Y) -#define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C; +#define BUILDSR() cpu.ccr = (cpu.ccr & 0xf0) | (N << 3) | (Z << 2) | (V<<1) | C; #define GETSR() \ c = (cpu.ccr >> 0) & 1;\ @@ -109,6 +109,8 @@ static int memory_size; +extern int iosimulation(cpu_state_type *cpu,int cycles); +extern void init_ioregs(cpu_state_type *cpu); static int get_now () @@ -326,6 +328,10 @@ bit = thisnib; } + else if (looking_for & (L_2 | IMM)) + { + plen = 1; + } else if (looking_for == E) { dst->op = q; @@ -458,7 +464,7 @@ } else { - printf ("Dont understand %x \n", looking_for); + printf ("Dont understand %x:%x \n", addr,looking_for); } } @@ -936,12 +942,13 @@ return 1; } + void sim_resume (sd, step, siggnal) SIM_DESC sd; { static int init1; - int cycles = 0; + static int cycles = 0; int insts = 0; int tick_start = get_now (); void (*prev) (); @@ -954,6 +961,7 @@ int pc; int c, nz, v, n; int oldmask; + int vector; init_pointers (); prev = signal (SIGINT, control_c); @@ -1012,6 +1020,15 @@ #endif + if ((vector=iosimulation(&cpu,cycles)) && !(cpu.ccr & 0x80)) + { + BUILDSR(); + cpu.regs[7]-=4; + SET_MEMORY_L(cpu.regs[7],(cpu.ccr<<24)|pc); + pc=GET_MEMORY_L(vector*(h8300hmode?4:2)); + cpu.ccr|=0x80; + goto top; + } cycles += code->cycles; insts++; switch (code->opcode) @@ -1370,32 +1387,24 @@ cpu.exception = SIGILL; goto end; case O (O_SLEEP, SN): - /* The format of r0 is defined by devo/include/wait.h. */ -#if 0 /* FIXME: Ugh. A breakpoint is the sleep insn. */ - if (WIFEXITED (cpu.regs[0])) - { - cpu.state = SIM_STATE_EXITED; - cpu.exception = WEXITSTATUS (cpu.regs[0]); - } - else if (WIFSTOPPED (cpu.regs[0])) + if (cpu.ccr & 0x80) { cpu.state = SIM_STATE_STOPPED; - cpu.exception = WSTOPSIG (cpu.regs[0]); + cpu.exception = SIGTRAP; + } else + while (cpu.state = SIM_STATE_RUNNING) { + if ((vector=iosimulation(&cpu,cycles)) && !(cpu.ccr & 0x80)) + { + usleep(100); + BUILDSR(); + cpu.regs[7]-=4; + SET_MEMORY_L(cpu.regs[7],(cpu.ccr<<24)|pc+2); + pc=GET_MEMORY_L(vector*(h8300hmode?4:2)); + cpu.ccr|=0x80; + goto top; + } + cycles++; } - else - { - cpu.state = SIM_STATE_SIGNALLED; - cpu.exception = WTERMSIG (cpu.regs[0]); - } -#else - /* FIXME: Doesn't this break for breakpoints when r0 - contains just the right (er, wrong) value? */ - cpu.state = SIM_STATE_STOPPED; - if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0])) - cpu.exception = SIGILL; - else - cpu.exception = SIGTRAP; -#endif goto end; case O (O_BPT, SN): cpu.state = SIM_STATE_STOPPED; @@ -1556,7 +1565,143 @@ } } goto next; - + case O (O_LDC, SB): + { + switch(GET_MEMORY_B(pc)) { + case 0x03: + cpu.ccr = GET_B_REG(code->src.reg); + break; + case 0x07: + cpu.ccr = code->src.literal; + break; + case 0x01: + { + switch(GET_MEMORY_B(pc+2)) { + case 0x69: + cpu.ccr = GET_MEMORY_W(GET_L_REG(code->dst.reg)); + break; + case 0x6f: + case 0x78: + code->src.type=X(OP_DISP,SW); + cpu.ccr = fetch (&code->src); + break; + case 0x6d: + code->src.type=X(OP_INC,SW); + cpu.ccr = fetch (&code->src); + break; + case 0x6b: + cpu.ccr = GET_MEMORY_W(code->src.literal); + break; + } + } + } + GETSR(); + } + goto next; + case O (O_STC, SB): + { + BUILDSR(); + switch(GET_MEMORY_B(pc)) { + case 0x02: + SET_B_REG(code->dst.reg,cpu.ccr); + break; + case 0x01: + switch(GET_MEMORY_B(pc+2)) { + case 0x69: + SET_MEMORY_W(GET_L_REG(code->dst.reg),cpu.ccr); + break; + case 0x6f: + case 0x78: + code->dst.type=X(OP_DISP,SW); + store (&code->dst,cpu.ccr); + break; + case 0x6d: + code->dst.type=X(OP_DEC,SW); + store (&code->dst,cpu.ccr); + break; + case 0x6b: + SET_MEMORY_W(code->dst.literal,cpu.ccr); + break; + } + } + } + goto next; + case O (O_EEPMOV, SB): + { + int cnt=GET_B_REG(4); + if(cnt==0) cnt=0x100; + while(cnt!=0) { + SET_MEMORY_B(cpu.regs[6],GET_MEMORY_B(cpu.regs[5])); + cpu.regs[5]++; + cpu.regs[6]++; + --cnt; + } + SET_B_REG(4,cnt); + } + goto next; + case O (O_EEPMOV, SW): + { + int cnt=GET_W_REG(4); + if(cnt==0) cnt=0x10000; + while(cnt!=0) { + SET_MEMORY_B(cpu.regs[6],GET_MEMORY_B(cpu.regs[5])); + cpu.regs[5]++; + cpu.regs[6]++; + --cnt; + } + SET_W_REG(4,cnt); + } + goto next; + case O (O_RTE, SN): + { + unsigned int frame; + frame = GET_MEMORY_L (cpu.regs[7]); + cpu.ccr=frame>>24; + GETSR(); + pc=frame & 0xffffff; + cpu.regs[7]+=4; + }; + goto end; + case O (O_TRAPA, SB): + { + int v; + v=GET_MEMORY_W(pc)>>4; + v&=3; + BUILDSR(); + cpu.regs[7]-=4; + SET_MEMORY_L(cpu.regs[7],(cpu.ccr<<24)|code->next_pc); + pc=GET_MEMORY_L(v*(h8300hmode?4:2)+0x08*(h8300hmode?4:2)); + cpu.ccr|=0x80; + }; + goto end; + case O (O_BKPT, SN): + /* The format of r0 is defined by devo/include/wait.h. */ +#if 0 /* FIXME: Ugh. A breakpoint is the sleep insn. */ + if (WIFEXITED (cpu.regs[0])) + { + cpu.state = SIM_STATE_EXITED; + cpu.exception = WEXITSTATUS (cpu.regs[0]); + } + else if (WIFSTOPPED (cpu.regs[0])) + { + cpu.state = SIM_STATE_STOPPED; + cpu.exception = WSTOPSIG (cpu.regs[0]); + } + else + { + cpu.state = SIM_STATE_SIGNALLED; + cpu.exception = WTERMSIG (cpu.regs[0]); + } +#else + /* FIXME: Doesn't this break for breakpoints when r0 + contains just the right (er, wrong) value? */ + cpu.state = SIM_STATE_STOPPED; + if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0])) + cpu.exception = SIGILL; + else + cpu.exception = SIGTRAP; +#endif + goto end; default: cpu.state = SIM_STATE_STOPPED; cpu.exception = SIGILL; @@ -2040,12 +2185,15 @@ struct _bfd *abfd; char **argv; { + char *ptyname; /* FIXME: Much of the code in sim_load can be moved here */ - sim_kind = kind; myname = argv[0]; sim_callback = ptr; /* fudge our descriptor */ + if((ptyname=openpty())!=NULL) + (*sim_callback->printf_filtered) (sim_callback, + "SCI0 = %s\n",ptyname); return (SIM_DESC) 1; } @@ -2055,8 +2203,9 @@ int quitting; { /* nothing to do */ + closepty(); } - + /* Called by gdb to load a program into memory. */ SIM_RC @@ -2125,6 +2274,7 @@ abort (); cpu.mask = memory_size - 1; + init_ioregs(&cpu); if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd, sim_kind == SIM_OPEN_DEBUG, 0, sim_write) diff -Nru gdb-5.0/sim/h8300/inst.h gdb-5.0-patch/sim/h8300/inst.h --- gdb-5.0/sim/h8300/inst.h Fri Apr 16 10:35:02 1999 +++ gdb-5.0-patch/sim/h8300/inst.h Tue Sep 25 10:27:15 2001 @@ -15,7 +15,7 @@ can only happen when simulating H8/300H programs). We make no attempt to catch overlapping addresses, wrapped addresses, etc etc. */ #define H8300_MSIZE (1<<16) -#define H8300H_MSIZE (1<<18) +#define H8300H_MSIZE (1<<24) #define CSIZE 1000 diff -Nru gdb-5.0/sim/h8300/io.c gdb-5.0-patch/sim/h8300/io.c --- gdb-5.0/sim/h8300/io.c Thu Jan 1 09:00:00 1970 +++ gdb-5.0-patch/sim/h8300/io.c Sun Dec 2 22:13:54 2001 @@ -0,0 +1,276 @@ +/* + H8 simulator Internal Peripheral Support +*/ + +#include +#include +#include +#include +#include + +#include "inst.h" + +#define SMR (cpu->memory[0xffffb0]) +#define BRR (cpu->memory[0xffffb1]) +#define SCR (cpu->memory[0xffffb2]) +#define TDR (cpu->memory[0xffffb3]) +#define SSR (cpu->memory[0xffffb4]) +#define RDR (cpu->memory[0xffffb5]) + +static int scifd=-1; +static struct termios old_attr; + + +static void +timer8(cpu_state_type *cpu,int cycles) +{ + int base[4]={0xffff80,0xffff81,0xffff90,0xffff91}; + int tm,cnt,cyc; + static int prescale8=8,prescale64=64,prescale8192=8192; + static unsigned int prev_cycle=0; + cyc=(unsigned int)cycles-prev_cycle; + prev_cycle=cycles; + prescale8-=cyc; + prescale64-=cyc; + prescale8192-=cyc; + if (prescale8<=0) + { + for(tm=0;tm<4;tm++) + if ((cpu->memory[base[tm]]&0x07)==1) + { + cnt=++cpu->memory[base[tm]+8]; + if (cnt>=0x100) + { + cpu->memory[base[tm]+2]|=0x20; + cnt=0; + } + cpu->memory[base[tm]+8]=cnt; + } + prescale8+=8; + } + if (prescale64<=0) + { + for(tm=0;tm<4;tm++) + if ((cpu->memory[base[tm]]&0x07)==2) + { + cnt=++cpu->memory[base[tm]+8]; + if (cnt>=0x100) + { + cpu->memory[base[tm]+2]|=0x20; + cnt=0; + } + cpu->memory[base[tm]+8]=cnt; + } + prescale64+=64; + } + if (prescale8192<=0) + { + for(tm=0;tm<4;tm++) + if ((cpu->memory[base[tm]]&0x07)==3) + { + cnt=++cpu->memory[base[tm]+8]; + if (cnt>=0x100) + { + cpu->memory[base[tm]+2]|=0x20; + cnt=0; + } + cpu->memory[base[tm]+8]=cnt; + } + prescale8192+=8192; + } + for(tm=0;tm<4;tm++) + if (cpu->memory[base[tm]+8]>=cpu->memory[base[tm]+4]) + { + cpu->memory[base[tm]+2]|=0x40; + if ((cpu->memory[base[tm]]&0x18)==0x08) + cpu->memory[base[tm]+8]=0; + } + for(tm=0;tm<4;tm++) + if (cpu->memory[base[tm]+8]>=cpu->memory[base[tm]+6]) + { + cpu->memory[base[tm]+2]|=0x80; + if ((cpu->memory[base[tm]]&0x18)==0x10) + cpu->memory[base[tm]+8]=0; + } +} + +static unsigned int complete_time(cpu_state_type *cpu,int cycles) +{ + int length; + int div[]={1,4,16,64}; + length=(SMR & 0x40)?7:8; + length+=(SMR & 0x20)?1:0; + length+=(SMR & 0x08)?1:0; + length+=2; + return length*32*div[SMR & 0x03]*BRR+cycles; +} + +static void send_data(int txd) +{ + char dt; + dt=txd; + write(scifd,&dt,1); + fsync(scifd); +} + +static int rcv_data(int *rxd) +{ + char rd; + if(read(scifd,&rd,1)>0) { + *rxd=rd; + return 1; + } else + return 0; +} + +static int sci(cpu_state_type *cpu,int cycles) +{ + static int tx_end_time=0; + static int rx_end_time=0; + int data; + if((SCR & 0x20) && !(SSR & 0x80)) { + send_data(TDR); + SSR |= 0x80; + tx_end_time=complete_time(cpu,cycles); + } + if(rcv_data(&data) && (SCR & 0x10) && ((rx_end_time==0) || (rx_end_time-cycles)<0)) { + if(SSR & 0x40) { + SSR |= 0x20; + } else { + RDR=data; + SSR |= 0x40; + } + rx_end_time=complete_time(cpu,cycles); + } + if((tx_end_time>0) && (tx_end_time-cycles)<0) { + if(SSR & 0x80) { + SSR |= 0x04; + } + } +} + +static int +intcont(cpu_state_type *cpu) +{ + struct INT_LIST { + int vector; + int isr_adr; + unsigned char isr_mask; + int ier_adr; + unsigned char ier_mask; + } int_table[]= { + {36,0xffff82,0x40,0xffff80,0x40}, + {37,0xffff82,0x80,0xffff80,0x80}, + {38,0xffff83,0x40,0xffff81,0x40}, + {38,0xffff83,0x80,0xffff81,0x40}, + {39,0xffff82,0x20,0xffff80,0x20}, + {39,0xffff83,0x20,0xffff81,0x20}, + {40,0xffff92,0x40,0xffff90,0x40}, + {41,0xffff92,0x80,0xffff90,0x80}, + {42,0xffff93,0x40,0xffff91,0x40}, + {42,0xffff93,0x80,0xffff91,0x40}, + {43,0xffff92,0x20,0xffff90,0x20}, + {43,0xffff93,0x20,0xffff91,0x20}, + {52,0xffffb4,0x38,0xffffb2,0x40}, + {53,0xffffb4,0x40,0xffffb2,0x40}, + {54,0xffffb4,0x80,0xffffb2,0x80}, + {55,0xffffb4,0x04,0xffffb2,0x04} + }; + int irqno; + for (irqno=0;irqnomemory[int_table[irqno].ier_adr]&int_table[irqno].ier_mask) + if(cpu->memory[int_table[irqno].isr_adr]&int_table[irqno].isr_mask) + return int_table[irqno].vector; + } + return 0; +} + +int +iosimulation(cpu_state_type *cpu,int cycles) +{ + timer8(cpu,cycles); + sci(cpu,cycles); + return intcont(cpu); +} + +void init_ioregs(cpu_state_type *cpu) +{ + struct INITTABLE { + int addr; + short data; + } reg_ini[] = { + 0xffff80,0x00, + 0xffff81,0x00, + 0xffff82,0x00, + 0xffff83,0x00, + 0xffff84,0xff, + 0xffff85,0xff, + 0xffff86,0xff, + 0xffff87,0xff, + 0xffff88,0x00, + 0xffff89,0x00, + 0xffff90,0x00, + 0xffff91,0x00, + 0xffff92,0x00, + 0xffff93,0x00, + 0xffff94,0xff, + 0xffff95,0xff, + 0xffff96,0xff, + 0xffff97,0xff, + 0xffff98,0x00, + 0xffff99,0x00, + 0xffffb0,0x00, + 0xffffb1,0xff, + 0xffffb2,0x00, + 0xffffb3,0xff, + 0xffffb4,0x84, + 0xffffb8,0x00, + 0xffffb9,0xff, + 0xffffba,0x00, + 0xffffbb,0xff, + 0xffffbc,0x84, + 0xffffc0,0x00, + 0xffffc1,0xff, + 0xffffc2,0x00, + 0xffffc3,0xff, + 0xffffc4,0x84, + }; + int c; + for(c=0;cmemory[reg_ini[c].addr]=reg_ini[c].data; +} + +char *openpty(void) +{ + const char nm[]="0123456789ABCDEF"; + static char ptyname[16]; + int c1,c2,fd; + struct termios attr; + for(c1='a';c1<='z';c1++) + for(c2=0;c2